Snooping During Split Locked Cycles; Snoop Write Back Cycles - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
WARNING
Proper system operation cannot be guaranteed if this restriction is not
met!
In order to insure that the above condition is met, system designers must compare the snoop
address to the locked address. If those addresses are in the same cache line, the snoop must be
blocked by the MBC. If the snoop and locked addresses are not in the same cache line, the
MBC can allow the snoop to complete.
5.1.2.5.1. Snooping During Split Locked Cycles
If CSCYC is high with CADS#, the cycle is split. Split cycles have adjacent virtual addresses,
but the physical addresses seen on the address bus are not necessarily adjacent. It is possible
that the physical addresses might be split across a page boundary. Obviously, split locked
cycles add another level of complexity to determining if the locked and snoop addresses are in
the same cache line.
The system designer can ensure that all locked data is aligned within a single cache line (in this
case CSCYC=O and there will never be split cycles!).
If
system software is not under the
complete control of the system designer, this may not be an option.
Before allowing snoops to occur during split locked cycles, system hardware designers must be
able to determine both of the physical addresses which the locked sequence will read and
write. If both addresses are known, snoops may be allowed to any other address. Snoops are
not allowed to the second address of a split locked sequence during accesses to the first address
and vice versa. BOTH addresses must be barred from snoops during the entire sequence!
5.1.2.6.
SNOOP WRITE BACK CYCLES
Snoop write back cycles are generated by the 82496 Cache Controller in response to a snoop
from the MBC which hits a modified line in the 82496 Cache Controller/82491 Cache SRAM
(and possibly also in the Pentium processor data cache). Snoop write back cycles are requested
by the 82496 Cache Controller by activation of SNPADS# instead of CADS#. For these
cycles, the 82496 Cache Controller only samples the CRDY# MBC response. The 82496
Cache Controller assumes that the memory bus controller owns the bus to perform the
intervening write back and that no other agents will snoop this cycle. This is called "Restricted
Back-Off Protocol" because a snoop write back cycle cannot be aborted by the CPU or the
MBC. Also, the 82496 Cache Controller will ignore CNA# during snoop write backs (no
subsequent cycle can be pipelined into a snoop write back cycle). Figure 5-16 shows the 82496
Cache Controller cycle progress signals required to request and complete a snoop write back
cycle.
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