Intel 82496 CACHE CONTROLLER User Manual page 56

PINOUTS
Table 1-10. Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions (Contd.)
Symbol Type Part Name and Function
WBA
0
CC The
Write back Buffer Address
pin is driven by the 82496 Cache
I CS Controller to indicate which line is loaded into the write-back buffer by the
82491 Cache SRAM for replacement write-backs. For snoop write-backs,
WBA indicates a snoop hit to the write-back buffer.
WBA shares a pin with the Optimized Interface Configuration signal
SEC2#
WBTYP
0
CC The 82496 Cache Controller
Write Back Cycle Type
pin is driven to the
I CS 82491 Cache SRAM to indicate a replacement write-back or snoop write-
back cycle.
WBTYP shares a pin with the Optimized Interface Configuration signal
LRO.
WBWE# 0 CC The 82496 Cache Controller
Write-Back Buffer Write Enable
pin is used
I
CS
in conjunction with the WBA and WBTYP pins to load the write-back
buffers of the 82491 Cache SRAM.
WBWE# shares a pin with the Optimized Interface Configuration signal
LR1.
WRARR#
0
CC
The 82496 Cache Controller
Write to 82491 Cache SRAM Array
signal
I CS
controls the writing of data into the 82491 Cache SRAM array and
updating of the MRU bit.
WWOR# I CC The
Weak Write Ordering Configuration
signal configures the 82496
Cache Controller into strong or weak write ordering modes. In strong
ordering mode, the chip set writes data to memory in the order in which it
was received from the Pentium processor. WWOR# shares a pin with the
82496 Cache Controller input signal MALE.
I
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