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HARDWARE INTERFACE
Relation to Other Signals
Table 5-9 lists the signals that are sampled at RESET. Note that a pin that outputs/inputs both
a configuration signal (during reset) and another signal changes its value from configuration
signal to non-configuration signalon the rising edge of the first clock after RESET deassertion.
For example, the pin that inputs CLDRV during reset will input BGT# on the rising edge of the
first clock after RESET is deasserted.
Table 5-9. Signals Sampled at
RESET
Pentium™ Processor Configuration Inputs
BUSCHK#
Must be LOW.
82496 Cache Controller Configuration Inputs
CNA#[CFGO]
CFGO-CFG2 are the configuration inputs that are sampled
SWEND# [CFG1]
by the 82496 Cache Controller cache to determine which configuration
KWEND# [CFG2]
it should operate in.
FLUSH#
Must be HIGH for proper Pentium processor/82496 Cache Controller operation.
BGT# [CLDRV]
Selects the driving strength of the 82496 Cache Controller/82491 Cache SRAM
interface buffers.
SYNC# [MALDRV]
Selects the memory address bus driver strength.
SNPCLK# [SNPMD]
Indicates the snooping mode.
MALE [WWOR#]
When low Selects weak write ordering
CRDY#[SLFTST#]
Invokes 82496 Cache Controller self-test if HIGHZ# high.
MBALE[HIGHZ#]
Tristates 82496 Cache Controller outputs if active with SLFTST#.
82491 Cache SRAM Configuration Inputs
MZBT#[MX4/8#]
Determines whether each 82491 Cache SRAM uses four or eight I/O pins on the
memory bus.
MSEL#[MTR4/8#]
Determines the number of memory bus transfers needed to fill each cache line.
MCLK[MSTBM]
Indicates the memory bus configuration: Strobed if high, Clocked if toggling.
MFRZ# [MDLDRV]
Selects the memory data bus driver strength.
MBE#[PAR#]
Configures the 82491 Cache SRAM as a parity storage device if active.
5-184
I
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