Cw/R - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.42.
CW/R#
CW/R# Cache Write/Read
Indicates whether current cycle is write or read.
Output from 82496 Cache Controller (pin F05)
Synchronous to CLK
Signal Description
CW/R#, CD/C# and CM/lO# are 82496 Cache Controller cycle definition signals. CW/R#
indicates whether the 82496 Cache Controller requests a read cycle or a write cycle.
When Driven
CW/R# is valid with CADS# and SNPADS# and remains valid until CRDY# or CNA# is
asserted.
Relation to Other Signals
Pin Symbol Relation to Other Signals
CADS# Address and cycle specification signals (I.e., APIC#, CCACHE#, CD/C#, CM/IO#,
CPCD, CPWT, CSCYC, CW/R#, CWAY, KLOCK#, MAP, MBT[3:0], MCACHE#,
MCFA, MSET, MTAG, NENE#, PALLC#, RDYSRC, and SMLN#) are valid with
CADS#.
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