Intel 82496 CACHE CONTROLLER User Manual page 178

HARDWARE INTERFACE
If an ADS# for a cycle which needs the memory bus has been previously issued, and the 82496
Cache Controller samples CNA# or CRDY# asserted (for a previous memory bus cycle), then
the 82496 Cache Controller will assert BLEC# for one CLK to latch the CPU byte enables. See
Figure 5-24.
ClK~
ADS# I
<
I
.REVIOU~
ADS#
~
I VAll! n·l Il®< I VALID n
BlEC#
CNA#
orCRDY#
MBE#
CADS#
~
CDB42
Figure 5-24. BLEC# Assertion Due to CNA# or CRDY# Assertion
If the ADS# cycle to the 82496 Cache Controller is a cache hit, then BLEC# will be asserted
immediately (i.e., it could be inactive for as short as one CLK as shown, or longer). See
Figure 5-25.
ClK
~
~
I GOES lOW IFA HIT
i
~ ~
. --.[
IN 82496 TAGRAM
I
I ~\J-.
~""",,,,*,,~
IVALlDn I
X0""~"'~'0J0t:""~~:<::'I
ADS#
BlEC#
MBE#
CDB43
Figure 5-25. BLEC# Assertion Due to Hit in 82496 Cache Controller Tag RAM
Relation to Other Signals
Pin Symbol
Relation to Other Signals
BLE# BLEC# is functionally identical to BLE#.
BE[7:0]#
BLEC# causes the CPU byte enables, BE[7:0]#, to be latched in the 82491 Cache
SRAM devices and driven out to the memory bus on the MBE# pins.
I
5-53