Intel 82496 CACHE CONTROLLER User Manual page 351

MEMORY BUS FUNCTIONAL DESCRIPTION
CNA# is sampled active (clock 5), indicating that the MBC is ready to schedule a new memory
bus cycle. In case the MBC does not support a pipelined interface with the 82496 Cache
Controller (CNA# always inactive), the BLEC# will remain inactive until CRDY# is sampled
active. Note that after CNA# activation, cycle control signals' are not guaranteed to be valid.
NA# (of cycle A) is activated after KWEND# (clock 6), in order to determine the state of
KEN# to the CPU (since KEN# is sampled by the CPU with NA# or first BRDY#). Note that
the CPU delays the new ADS# due to AHOLD activation.
The CPU issues an ADS# in clock 10 (cycle B). This read cycle also misses the cache
directory. Since the 82496 Cache Controller already sampled CNA# active (clock 5) it
activates a new CADS# (clock 12) before the CRDY# of the current memory bus cycle, (Le.
this cycle is pipelined in the MBC).
Note that once the cycle progress signals (BGT#, CNA#, KWEND#, SWEND#) of a cycle are
sampled active, the 82496 Cache Controller ignore them until the CRDY# of that cycle. The
82496 Cache Controlle.r does not pipeline the cycle progress signals, i.e for a pipelined access
(cycle B), it will start sampling them (clock 16) after the CRDY# of the current memory bus
cycle (A).
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