Intel 82496 CACHE CONTROLLER User Manual page 38

PINOUTS
Table 1-10. Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions (Contd.)
Symbol Type Part Name and Function
APCHK#
0
P This is the address parity check status pin. APCHK# is asserted two
clocks after EAOS# is sampled active if the Pentium processor has
detected a parity error on the address bus during 82496 Cache Controller
inquire cycles. APCHK# will remain active for one clock each time a parity
error is detected.
APERR# 0
CC The Address Parity Error output indicates that the 82496 Cache
Controller has detected a CPU bus address parity error.
APIC#
0
CC The Advanced Programmable Interrupt Controller Address Decoding
output indicates, when active, that the current address is an APIC address
(ie. 0 FE EO 00 00 to 0 FE EO 03 FF Hex).
BE# I CS The Byte Enable pins are used to determine which bytes must be written
BE[7:0]#
0
P to external memory, or which bytes were requested by the CPU for the
current cycle. The byte enables are driven in the same clock as the
address lines (A[31 :3]). One Pentium processor byte enable output,
BE[7:0]#, is connected to either one or two (cache size dependent) 82491
Cache SRAM BE# input. When a 82491 Cache SRAM is configured to
be a parity device, the CPU byte enables are connected to the 82491
Cache SRAM COATA[7:4] pins (BE[7:4]# to one parity 82491 Cache
SRAM, and BE[3:0]# to the other).
BGT# I CC Bus Guaranteed Transfer is generated by the Memory Bus Controller
(MBC) to indicate that it is committed to completing a given memory bus
cycle. Until BGT# is active, the 82496 Cache Controller owns the cycle
and may abort the cycle upon an intervening bus snoop. Once BGT# is
asserted, the MBC owns the cycle, freeing the 82496 Cache Controller for
other operations.
BGT# shares a pin with the Configuration signal ClORV.
BlAST#
0
CC The Burst last signal indicates the end of a burst cycle when it comes
I
CS
together with BROY# or BROYC#.
BlE#
0
CC The 82496 Cache Controller asserts Byte latch Enable to latch PCO,
PWT, BEO#-BE7#, CACHE# and SCYC from the CPU into an external
377-type latch. This signal is not necessary with the 82496 Cache
Controller 182491 Cache SRAM secondary cache since those signals are
latched into the 82496 Cache Controller and 82491 Cache SRAM de-
vices.
BlEC#
0
CC The 82496 Cache Controller asserts Byte Latch Enable to the 82491
I CS Cache SRAM to latch the Pentium processor byte enables (BE[7:0]#). If
active (LOW), the 82491 Cache SRAM will latch new byte enable data
upon the rising edge of ClK. If inactive (HIGH), the latch will be closed.
BOFF#
0
CC The Back-Off Pentium processor signal is driven by the 82496 Cache
I CS Controller to resolve In response to BOFF#, the Pentium processor and
I P 82491 Cache SRAM (if driving COAT A lines to the Pentium processor)
will float their buses on the next ClK. The CPU remains in bus hold until
BOFF# is negated, at which time the Pentium processor restarts the
aborted bus cycles.
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