With Replacement Of Modified Line - Intel 82496 CACHE CONTROLLER User Manual

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MEMORY BUS FUNCTIONAL DESCRIPTION
6.1.2.2. WITH REPLACEMENT OF MODIFIED LINE
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Figure 6-3. Read Miss with Replacement of Modified Line
Figure 6-3 illustrates CPU read cycles (A, B) that miss the 82496 Cache Controller cache, and
require the replacement of two modified lines (tag replacement, lines/sector=l, line ratio=1).
In clock 1, the Pentium processor issues an ADS# of a memory read cycle. In clock 2, a miss is
detected, so CADS# (also CDTS#) and cycle control signals are driven to the MBC on clock 3.
BUS# and MCYC# are pulsed active to the 82491 Cache SRAM.
Since the cache directory look-up indicates that a modified line has to be replaced, AHOLD
goes active in clock 3. After BGT# is received for the read cycle (clock 4), the 82491 Cache
SRAM write-back buffer is prefilled with the contents of the ARRAY locations corresponding
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