Intel 82496 CACHE CONTROLLER User Manual page 286

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HARDWARE INTERFACE
5.2.2.100. MSEL#
MSEL# Memory Buffer Chip Select
Selects 82491 Cache SRAM SRAMs, initiates MZBT# sampling.
Input to 82491 Cache SRAM (pin 25)
Synchronous to MCLK or asynchronous (strobed mode)
Signal Description
MSEL# is a 82491 Cache SRAM input providing three main functions:
1. MSEL# active qualifies the MBRDY# input to the 82491 Cache SRAM. If MSEL# is
inactive, MBRDY# is not recognized.
2. MSEL# inactive causes MZBT# to be sampled for the next transfer. MSEL# going active
latches the MZBT# value for the next transfer.
3. MSEL# going inactive initializes the 82491 Cache SRAM's internal memory burst counter
(the value depends upon the sampled value of MZBT#).
The data portion of the 82491 Cache SRAM contains a memory burst counter that counts
through the CPU burst order with each MBRDY# assertion (or MISTB or MOSTB transition)
and increments a pointer to the memory buffer being accessed.
MSEL# going inactive resets this burst counter to its original burst value if MZBT# was
sampled inactive. By resetting this counter before MEOC# assertion, the memory bus can write
over the data that was latched into the memory cycle buffers. This would be necessary if the
MBC began latching data from main memory prior to the snoop window closure, and the
snoop result was a hit to a modified line in another cache.
MSEL# may stay inactive for single transfer cycles such as posted 64-bit write cycles. Once
active, MSEL# need not go inactive because the burst counter is RESET with MEOC#
activation. Since MZBT# may also be sampled with MEOC#, it is possible to leave MSEL#
asserted throughout most basic transfers.
MSEL# or MEOC# must be used to reset the burst counter before any transfer begins. If
transfers have begun (due to a very fast memory subsystem) and are interrupted (for example,
by a snoop hit to [M] before BGT# assertion), MSEL# must be brought inactive so the burst
counter may be reset for the snoop-write-back. MSEL# must be sampled inactive for at least
one MCLK after RESET. This resets the memory burst counter for the first transfer.
When Sampled
In clocked memory bus mode, MSEL# is sampled with every rising edge of MCLK. In this
mode, if MSEL# is sampled inactive, the memory burst counter is RESET and MZBT# is
sampled. If MSEL# is sampled active and MBRDY# is sampled active, the memory burst
counter is incremented. Since it is constantly sampled with MCLK, MSEL# must always be
driven to a known state and must always meet set-up and hold times to every MCLK edge.
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