Mbt[3:0] - Intel 82496 CACHE CONTROLLER User Manual

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HARDWARE INTERFACE
5.2.2.84. MBT[3:0]
MBT[3:0] Memory Branch Trace Address bits
Provides bits 0-2 of the branch target linear address and the default operand size
during a Branch Trace Message Special Cycle.
Output from 82496 Cache Controller (pins: U10, U12, U14, U16)
Synchronous to ClK
Signal Description
The Memory bus branch trace pins, MBT[3:0], echo the Pentium processor bus branch trace
pins. They provide bits 0-2 of the branch target linear address and the default operand size
during a Branch Trace Message Special Cycle to the Memory Bus Controller.
MBTO:
MBTl:
MBT2:
MBT3:
Pentium processor Address bit AO of the branch target linear address
Pentium processor Address bit Al of the branch target linear address
Pentium processor Address bit A2 of the branch target linear address
Driven high if the default operand size is 32 bits
Driven low if the default operand size is 16 bits
The Branch Trace Message Special Cycle is part of the Pentium processor execution tracing
protocol. If the execution tracing enable bit (bit 1) in TRI2 is set to 1, a branch trace message
special cycle will be driven each time IBT is asserted (i.e., whenever a branch is taken).
When Driven
The MBT[3:0] outputs are driven to their valid levels with the CADS# of a branch trace
message special cycle. These outputs remain valid until CAHOLD is asserted or the clock after
the earlier of CNA# or CRDY#.
During normal operation, the 82496 Cache Controller MBT[3:0] pins may be left unconnected
or connected to the memory bus.
If the MBT[3:0] pins are connected between the memory bus and the 82496 Cache
Controller, the MBC must always drive MBT[3:0] low during inquire and back-invalidation
cycles.
If the MBT[3:0] pins are left unconnected between the 82496 Cache Controller and the
memory bus, external pull-downs must be connected to the MBT[3.0] pins of the 82496
Cache Controller.
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