Mcfa[6:0]. Mset[10:0]. Mtag[11 :0] - Intel 82496 CACHE CONTROLLER User Manual

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ntel
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HARDWARE INTERFACE
5.2.2.86.
MCFA[6:0], MSET[10:0], MTAG[11 :0]
MCFA[6:0] Memory Address Bus
MSET[10:0] Memory address bus pins.
MTAG[11:0] Input/Output between Memory Bus and 82496 Cache Controller (pins Q14, Q15,
Q16,R07,S05,P15,R17, R12,R13,Q11,T18,S18,R14,S17, R15,Q12,Q13,
R16,Q08, R08,T17,Q09,T16, T15,S16,R09,S15,R10,Q10,R11)
Input synchronous to ClK, SNPClK or SNPSTB#;
Output synchronous to ClK, MAOE# active and MALE high.
Signal Description
MSET, MTAG, MCFA comprise the 82496 Cache Controller cache memory address bus.
They pass through an output latch on the 82496 Cache Controller which can be controlled by
the MBC using the signals MALE, MBALE, MAOE# and MBAOE#. MBALE and MALE are
the address latch enables for the sub-line address portion and the line address portion,
respectively. MBAOE# and MAOE# are the address latch output enables for the sub-line
address and the line address portions of the address respectively.
When MAOE# and MBAOE# are active, MSET, MTAG, MCFA are driven by the 82496
Cache Controller cache. MSET, MTAG, MCFA are valid at the start of a memory bus cycle at
the input of the address latch in the 82496 Cache Controller. If MALE and MBALE are HIGH
(flow-through) and MAOE# and MBAOE# are active (outputs enabled), the address is driven
to the memory bus with CADS# and SNPADS#.
If a new cycle starts and MALE and MBALE are low, and MAOE# and MBAOE# are also
low, the previous address remains valid on the address pins of the 82496 Cache Controller
cache controller. Once MALE/MBALE goes HIGH, the new address flows through with the
appropriate propagation delay (MSET, MTAG, MCFA address valid delay from
MALE/MBALE going HIGH). The new address appears at the 82496 Cache Controller
outputs if MAOE# and MBAOE# are both active.
If a new cycle starts and MALE and MBALE are HIGH while MAOE# and MBAOE# are
inactive, the 82496 Cache Controller's MSET, MTAG, MCFA outputs remain in the high-
impedance state. Once MAOE# and MBAOE# are asserted, the new address flows through
with the appropriate propagation delay (MSET, MTAG, MCFA address valid delay from
MAOE#/MBAOE# going active).
MSET, MTAG, MCFA are used as 82496 Cache Controller inputs (with MAOE# and
MBAOE# inactive) during snoop cycles. These address lines are sampled by the 82496 Cache
Controller during snoop initiation along with the other snoop attributes.
When Sampled/Driven
If MALE and MBALE are HIGH and MAOE# and MBAOE# are low, MSET, MTAG, MCFA
are valid with CADS# and SNP ADS# with the timing referenced to CLK. Otherwise, they are
asserted with a delay from MALE/MBALE HIGH or MAOE#/MBAOE# active.
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