Cahold - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.27.
CAHOLD
CAHOLD Cache AHOlD Output
AHOlD output and self-test result.
Output from 82496 Cache Controller (pin H05)
Synchronous to ClK
Signal Description
CAHOLD reflects the AHOLD input to the Pentium processor (which is generated by the
82496 Cache Controller).
When the Pentium processor AHOLD is asserted, CAHOLD is also asserted. CAHOLD can be
monitored by the MBC to determine when the 82496 Cache Controller is performing CPU
inquires and back-invalidations.
It
can also be used to determine when to return BRDY# to the
CPU for Flush and Write Back special cycles.
CAHOLD is used during 82496 Cache Controller self-test to indicate the pass/fail condition.
It
can be sampled in the CLK after the deassertion of FSIOUT# to determine the success or
failure of BIST. CAHOLD high indicates the successful completion of BIST.
When Driven
CAHOLD is always at a valid logic level. CAHOLD is asserted whenever AHOLD is asserted
to the CPU.
During BIST, CAHOLD is driven low immediately upon the detection of an error (even before
FSIOUT# goes inactive).
Relation to Other Signals
Pin Symbol Relation to Other Signals
AHOlD Except during 82496 Cache Controller self-test, CAHOlD reflects the value of
AHOlD (with no delay).
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