Intel 82496 CACHE CONTROLLER User Manual page 366

Volume 2: 82496 cache controller and 82491 cache sram data book
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MEMORY BUS FUNCTIONAL DESCRIPTION
6.5.
1/0 CYCLES
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CDB63
NOTE:
1_
In strobed mode, MISTS/MOSTS are used in place of MSRDY to indicate data transfer ont%ff
of the memory bus_
Figure 6-10. 1/0 Cycles
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6·21

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