Intel 82496 CACHE CONTROLLER User Manual page 335

HARDWARE INTERFACE
5.2.2.140. TRST#
TR8T# Test Logic Reset
Allows the TAP controller to be asynchronously initialized.
Input to Pentium processor (pin 818) and 82496 Cache Controller (pin T02)
Asynchronous
Pentium processor and 82496 Cache Controller internal Pull-ups
Signal Description
TRST# is a test logic control pin. When asserted, it will force the TAP controller into the Test
Logic Reset State (see the TAP controller state diagram, Figure 11-3).
When in Test-Logic-Reset State, the test logic is disabled so that normal operation of the
device can continue unhindered. During initialization, the Pentium processor or 82496 Cache
Controller initializes the instruction register such that the IDCODE instruction is loaded.
On power up, the TAP controller is automatically initialized to the test logic reset state (test
logic disabled), so normal Pentium processor, 82496 Cache Controller, or 82491 Cache SRAM
behavior is the default. The Test Logic Reset State is also entered when TRST# is asserted
(Pentium processor or 82496 Cache Controller), or when TMS is high for 5 or more
consecutive clocks (Pentium processor, 82496 Cache Controller, or 82491 Cache SRAM).
When Sampled
TRST# is an asynchronous input.
Relation to Other Signals
None.
NOTE
Refer to the Pentium™ Processor Data Book for additional details.
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