Mbrdy - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.83.
MBRDY#
MBRDY# Memory Burst Ready
Burst ready input to the memory buffers.
Input to 82491 Cache SRAM (pin 22)
Synchronous to MCLK
Signal Description
In clocked memory bus mode, MBRDY# is used with MSEL# active to advance the memory
burst address counter of the memory buffer in use. As a result, new data is latched from the
memory bus (read cycle) or new data is driven from the 82491 Cache SRAM memory cycle
buffer (write cycle). MBRDY# is sampled on all MCLK edges in which MSEL# is sampled
active and has no relation to CLK. In strobed mode, MISTB/MOSTB strobes data into and out
of the 82496 Cache Controller/82491 Cache SRAM.
For write cycles, the first piece of write data is available at the MDATA bus pins. MBRDY#
assertion with MSEL# active causes the next 64- or 128-bit slice of write data to be available.
If only one slice is required to be read or driven, MSEL# and MBRDY# need not go active.
For read cycles, the first piece of read data flows through to the CPU (if no MZBT#).
MBRDY# assertion with MSEL# activation causes the next slice of memory data to be latched
in the memory buffer. The assertion of BRDY# allows this data to be available on the CPU bus
and latches the previous doubleword into the CPU. For cacheable cycles, MBRDY# must be
asserted four or eight times, depending on cache configuration. MEOC# can replace the last
MBRDY# to latch the last slice of data into the 82491 Cache SRAM buffer. MBRDY# causes
the memory burst counter to be incremented. MEOC# resets the memory burst counter.
When Sampled
MBRDY# is sampled on
all
MCLK edges in which MSEL# is sampled active. In this way,
MSEL# qualifies the MBRDY# input. If MSEL# is sampled inactive, MBRDY# need not
follow MCLK set-up and hold times.
Once the maximum number of MBRDY# signals have been asserted to the 82491 Cache
SRAM, MBRDY# is ignored.
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