Intel 82496 CACHE CONTROLLER User Manual page 365

MEMORY BUS FUNCTIONAL DESCRIPTION
The CPU does not guarantee that the same cycle which was aborted will be issued after
completing the inquire sequence. Thus, BLEC# is activated together with the BOFF# (clock
11). BLEC# is deactivated again (clock 20) after sampling the re-issued (in this example)
ADS# in clock 19.
After the Pentium processor write-back has completed (clock 17), the CPU issues (in this
example, re-issues) the read miss cycle (clock 19). In clock 21 the MBC activates CRDY#
indicating the 82496 Cache Controller the completion of the write-back cycle on the memory
bus. As a result, the 82496 Cache Controller deactivates SNPBSY# (clock 22) and issues the
pending read miss cycle (activates CADS#, CDTS# in clock 22).
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