Intel 82496 CACHE CONTROLLER User Manual page 362

MEMORY BUS FUNCTIONAL DESCRIPTION
In clock 8, an ADS# of a write cycle is issued. Since this is the last locked cycle, LOCK# is
deactivated one clock after BLAST#.BRDYC# (clock 10). The locked write is posted like any
other memory write cycle, thus the 82496 Cache Controller supplies the BRDYC# to the CPU
(clock 9). The 82496 Cache Controller issues CADS# with active KLOCK# for the write cycle
(clock 10). Since LOCK# is deactivated, the 82496 Cache Controller deactivates KLOCK# one
clock after CADS# (clock 11), indicating that the MBC can release the memory bus after
completion of the current cycle.
In clock 11 a similar locked sequence starts (C,D). Since the last locked write was posted, a
new ADS# is issued even before the CRDY# of that write (clock 12). The 82496 Cache
Controller samples CNA# active (clock 11) and issues CADS# (clock 13). Note that the 82496
Cache Controller deactivates KLOCK# between unlocked operations for at least one clock (in
this example it is inactive for two clocks: 11 and 12).
In this example, SCYC (and, correspondingly, CSCYC) would be inactive (low) with ADS#
(CADS#) to indicate that the locked sequence is not split across a cache line boundary. If the
cycle is split, there would be multiple read cycles followed by multiple write cycles for the
split locked sequence.
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