Intel 82496 CACHE CONTROLLER User Manual page 41

PINOUTS
Table 1-10. Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions (Contd.)
Symbol Type Part Name and Function
ClDRV I CC
During RESET, the Cache Low Drive Configuration signal determines the
driving strength of the connections between the 82496 Cache Controller
and 82491 Cache SRAM components.
ClDRV shares a pin with the 82496 Cache Controller input signal BGT#.
ClK I
CC
The Clock input provides the fundamental timing for the Pentium
I
CS
processor, 82496 Cache Controller, and 82491 Cache SRAM components.
I P Its frequency is the internal operating frequency of the Pentium processor,
82496 Cache Controller, and 82491 Cache SRAM, and requires TTL levels.
All external timing parameters except TDI, TDO, TMS, and TRST# are
specified with respect to the rising edge of ClK. The clock inputs must be
provided with minimal skew between devices.
CM/IO#
0 CC
Cache Memory/IO is driven by the 82496 Cache Controller to indicate
whether a requested memory bus cycle is for memory or for I/O.
CNA# I
CC
Cache Next Address Enable is driven by the memory bus controller to
dynamically pipeline the 82496 Cache Controller cycles. If a cycle is
pending and CNA# is given, a new CADS# is driven with the new cycle in-
formation.
CNA# shares a pin with the Configuration signal CFGO.
CPCD
0
CC 82496 Cache Controller Page Cache Disable is a latched version of the
Pentium processor PCD attribute to give the memory bus controller direct
access. CPCD is valid with CADS# and SNPADS#.
CPWT 0
CC
82496 Cache Controller Page Write-Through is a latched version of the
Pentium processor PWT attribute to give the memory bus controller direct
access. CPWT is valid with CADS# and SNPADS#.
CRDY# I CC Cache Memory Bus Ready is generated by the memory bus controller to
I CS indicate to the 82496 Cache Controller and 82491 Cache SRAM that a
memory bus cycle has completed and the devices should make resources
available for the next cycle.
The 82496 Cache Controller CRDY# input signal shares a pin with the
Configuration signal SlFTST#.
CCCYC
0
CC
82496 Cache Controller Split Cycle Indication is a latched version of the
Pentium processor SCYC attribute to give the memory bus controller direct
access. CSCYC is active only for locked cycles with SCYC active, and inac-
tive for all others. CSCYC is valid with CADS# and SNPADS#.
CW/R# 0
CC Cache Write/Read is driven by the 82496 Cache Controller to indicate a
requested memory bus cycle requires a read or a write.
CWAY 0 CC Cache Way is driven by the 82496 Cache Controller to indicate to the
memory bus controller in which cache "way" the line will be loaded during
line fills or driven from during write-backs. CWAY is valid with CADS# and is
used to facilitate external tracking tags.
D/C# I CC
The Data/Code signal is one of the primary bus cycle definition pins. It is
0 P driven valid in the same clock as the ADS# signal is asserted. D/C#
distinguishes between data and code or special cycles.
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