Intel 82496 CACHE CONTROLLER User Manual page 296

HARDWARE INTERFACE
driven low to the CPU.
For cacheable hit cycles, NA# is issued once the caching attributes (KEN# & WB/WT#) are
ready on the CPU pins.
In all cases, the 1.5 deep pipeline rule will be met.
Relation to Other Signals
Pin Symbol Relation to Other Signals
BLAST#, The ClK in which NA# is issued to the CPU is dependent on the following signals:
BRDY(C)#, KWEND#, CNA# (which ·affects BlEC# and MBE#), BRDYC#*BlAST#, or
CNA#,
BRDY#*BlAST#.
KWEND#
I
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