Intel 82496 CACHE CONTROLLER User Manual page 360

MEMORY BUS FUNCTIONAL DESCRIPTION
Figure 6-7 illustrates a 82496 Cache Controller/82491 Cache SRAM write miss cycle which
follows the write to main memory with an allocation cycle. The example assumes that
allocating the new line requires the replacement of a modified line (write-back to main
memory). This example displays a configuration of 1 line per sector and a line ratio of 1: 1.
In clocks 1-3, the first write (cycle A) is posted in the 82491 Cache SRAM's memory-cycle
buffer, which was empty prior to that time. The write is completed without wait-states. NA# is
activated with the cache directory look-up (blind NA#), i.e. in clock 2. MCYC# is activated by
the 82496 Cache Controller to indicate to the 82491 Cache SRAM that this cycle will involve
the memory bus. In clock 3, CADS# and cycle control signals are issued. RDYSRC is low
indicating that the 82496 Cache controller is the source of the BRDY#s supplied to the CPU
(the MBC will not provide BRDY#s for this cycle). PALLC# is low indicating a potential
allocate cycle immediately following the write-through cycle. CNA# is active in clock 5
indicating the MBC is free to accept a new CADS#. Nevertheless, the 82496 Cache Controller
will not issue a new CADS# until after it resolves the allocatability of the current memory
write cycle.
MKEN# is sampled active during KWEND# (clock 6), indicating that the missed line should
be allocated in the 82496 Cache Controller/82491 Cache SRAM. Thus, the 82496 Cache
Controller issues a second CADS# (LF) to request the line allocation (note MCACHE#,
RDYSRC and CW /R#).
Concurrently with the memory bus write, the Cache Controller serves a CPU read hit (cycle B
in clocks 4 to 9 - note the wait state in clock 10 due to the write-after-read back to back
cycles on the CPU bus). In clock 8, the CPU starts a write cycle
(C),
but since it misses the
cache, its service waits for the BGT# of the allocation. This wait is due to the fact that until
BGT# activation, a snoop could happen, thus the usage of the 82491 Cache SRAM's CPU
buffer is not allowed. The last BRDYC# of this cycle (C) can be issued only after the CRDY#
of the allocation.
In clock 11, BGT# of the allocation is returned active. The cache controller activates AHOLD
in clock 12 to inquire the CPU. The cache controller also drives WBWE#, WBTYP, and WBA
to load the SRAM's write-back buffer from the ARRAY. The line is inquired in clock 15 (the
82496 Cache Controller drives the inquired address, activates INV and pulses EADS#).
HITM# is sampled inactive in clock 17, so the data will come from the 82491 Cache SRAM's
replacement write-back buffer. AHOLD is deactivated in clock 18 as a result of the Pentium
processor cache miss (HITM# inactive).
The 82496 Cache Controller notifies the 82491 Cache SRAM on allocations by pulsing the
MA WEA# signal after sampling an active MKEN# during KWEND# (clock 6). Note that the
CDTS# of the write-back cycle is not asserted with CADS# since the data is not available in
the 82491 Cache SRAM's write-back buffer till the BLAST#.BRDYC# of the inquire cycle or
the CLK following HITM# results.
Cycle D (a read hit in the 82496 Cache Controller) is handled concurrently with the 82496
Cache Controller replacement write back and cycle C handling on the memory bus (clocks 11-
22). The CPU bus data transfers for cycle D are delayed due to AHOLD assertion from the
inquire cycle.
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