Memory Bus Control Signals - Intel 82496 CACHE CONTROLLER User Manual

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HARDWARE INTERFACE
5.1.6.4. MEMORY BUS CONTROL SIGNALS
The main memory bus control signals, used to control the 82491 Cache SRAM's data path,
buffers and MUXes, are BRDY#, MSEL#, MEOC#, MBRDY# and CRDY#.
MSEL# enables the 82491 Cache SRAM memory interface and qualifies the MBRDY# signal.
If MSEL# is inactive, MBRDY# is not recognized. MSEL# is also used to reset the memory
burst counter. If MSEL# becomes inactive, the counter is initialized to its starting value.
MSEL# may remain active for many cycles or for all cycles, but it must be inactive for some
time after RESET (1 CLK is sufficient) to initialize the memory burst counter the first time.
The MBC asserts MEOC# to finish with the current buffer and switch the memory bus to the
next buffer to be used. MEOC# latches the last data segment (if not all MBRDY#s were given)
and loads the memory burst counter with the next address before switching to the new buffer.
MBRDY# is used to increment the memory burst counter to select the next data slice.
MBRDY# strobes data out of the 82491 Cache SRAM during write cycles and loads data into
the 82491 Cache SRAM during read cycles. MBRDY# is ignored by the 82491 Cache SRAM
when MSEL# is inactive
CRDY# completes the current cycle. When CRDY# is asserted, the 82491 Cache SRAM
discards the buffer contents used in the current cycle and, on line-fills and allocations, loads
the data into the 82491 Cache SRAM (cache SRAM) array. CRDY# must be asserted with or
sometime after MEOC# has been asserted for a particular cycle. CRDY# is synchronous to the
CPU clock but not to the memory clock. MEOC# is provided to allow the cycle to end on the
memory bus and to allow a new cycle to begin before it is synchronized as the CRDY# input.
An example of the 82491 Cache SRAM read data path is shown in Figure 5-20. The path
between the CPU and the memory bus is "flow-through" rather than clocked. Each line of data
in the CPU bus buffer is available at the memory buffer after some propagation delay.
Likewise, each line of data in the memory buffer is available in the CPU buffer. Data is burst
into and out of the memory buffer using MBRDY# or MISTB/MOSTB. Data is burst into and
out of the CPU buffer using BRDY#. In this way, there is no need for synchronization between
the memory and CPU data paths.
During a CPU line fill, data may be returned to the CPU in two ways. First, when the memory
buffer fills a 64-bit slice (with one MBRDY#), BRDY# may be asserted during the following
clock to burst the line back to the CPU. Second, the memory buffer may be filled completely
first (with four or eight MBRDY#s), and then BRDY# asserted on four consecutive clocks to
burst data back to the CPU.
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