Memory Address Bus And Address Control Signals; Memory Data Bus And Data Control Signals; Cache Synchronization Signals; Cpu Signals - Intel 82496 CACHE CONTROLLER User Manual

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HARDWARE INTERFACE
5.2.1.5. MEMORY ADDRESS BUS AND ADDRESS CONTROL SIGNALS
MALE, MAOE#, MBALE, MBAOE#, MBE#[7:0], MBT[3:0], MCFA[6:0], MSET[1O:0],
MTAG[1l:0], MAP, MAPERR#
5.2.1.6.
MEMORY DATA BUS AND DATA CONTROL SIGNALS
MBRDY#(MISTB), MDATA[7:0], MDOE#, MEOC#, MFRZ#, MOCLK(MOSTB), MSEL#,
MZBT#
5.2.1.7. CACHE SYNCHRONIZATION SIGNALS
FLUSH# (82496 Cache Controller), FSIOUT#, SYNC#
5.2.1.8. CPU SIGNALS
A20M#, APCHK#, BP[3:2], BP/PM[I:0], BRDY#, BREQ, BUSCHK#, CLK, FERR#,
FLUSH# (Pentium processor), FRCMC#, HIT#, HLDA, HOLD, IBT, IERR#, IGNNE#, INIT,
INTR, IU, IV, NMI, PCHK#, PEN#, PRDY, RlS#, RESET, SM!, SMIACT#
5.2.1.9. TEST SIGNALS
TCK, TDI, IDO, TMS, TRST#
5.2.1.10. PENTIUM PROCESSOR BUS OPTIMIZED INTERFACE SIGNALS
A[31:3] (Pentium processor), A[15:0] (82491 Cache SRAM) ADS#, ADSC#, AHOLD, AP,
BE[7:0]#, BOFF#, BRDYC#, BRDYC1#, BT[3:0], CACHE#, CDATA[7:0], CFA[6:0], D/C#,
D[63:0], DP[7:0], EADS#, EWBE#, HITM#, INV, KEN#, LOCK#, M/IO#, NA#, PCD, PWT,
SCYC, SET[1O:0], TAG[1l:0], W/R#, WB/WT#
5.2.1.11. 82496 CACHE CONTROLLER/82491 CACHE SRAM OPTIMIZED
INTERFACE SIGNALS
BLAST#, BLEC#, BRDYC2#, BUS#, MA WEA#, MCYC#, WAY, WBA[SEC2#],
WBTYP[LRO], WBWE#[LR1], WRARR#
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