Strobed Snooping Mode - Intel 82496 CACHE CONTROLLER User Manual

SNPClK
SNPSTB#
SNPINV
SNPNCA
MSET,MTAG,
MCFA,MAP
MBADE#
MADE#
ClK
SNPCYC#
MTHIT#
MHITM#
SNPBSY#
Figure 5-5. Clocked Snoop Mode
5.1.2.1.3. Strobed Snooping Mode
HARDWARE INTERFACE
CDB34
In strobed snooping mode (Figure 5-6), no clocks are needed to initiate the snoop. The snoop
address, address parity, and snoop parameters are sampled with the falling edge of SNPSTB#,
and the 82496 Cache Controller begins the snoop once it has synchronized this information
internally. Synchronization requires an additional two CPU CLK cycles.
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