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Intel Manuals
Computer Hardware
80386
Reference manual
Intel 80386 Reference Manual
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Hardware reference manual
(308 pages)
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Contents
Table of Contents
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Table of Contents
Table of Contents
Table of Contents
Figure Title Page
Refresh Interval Counter PAL
Refresh Address Counter PAL
Tables
Customer Support
System Overview
Microprocessor
80386 System Components
80386 System Block Diagram
Corprocessors
DMA Controller
Interrupt Controller
Clock Generator
Internal Architecture
Instruction Pipelining
80386 Functional Units
Code Prefetch Unit
Execution Unit
Segmentation Unit
Paging Unit
Local Bus Interface
Bus Operations
Summary of 80386 Signal Pins
Bus Cycle Definitions
Bus States
32-Bit Data Bus Transfers and Operand Alignment
Clk2 and Clk Relationship
Pipelined Address Cycles
80386 Bus States Timing Example
Bus State Diagram (Does Not Include Address Pipelining)
Non-Pipelined Address and Pipelined Address Differences
Consecutive Bytes in Hardware Implementation
Address, Data Bus, and Byte Enables for 32-Bit Bus
Possible Data Transfers on 32·Bit Bus
Read Cycle
Misaligned Transfer
Non-Pipelined Address Read Cycles
Misaligned Data Transfers on 32-Bit Bus
Write Cycle
Pipelined Address Cycle
Non-Pipelined Address Write Cycles
Interrupt Acknowledge Cycle
Interrupt Acknowledge Bus Cycles
B516 Cycle
16-Bit Byte Enables and Operand Alignment
Internal NA# and BS16# Logic
32-Bit and 16-Bit Bus Cycle Timing
Bus Timing
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Instruction Pipelining
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