Pentium™ Processor Cpu-Cache Chip Set Brief Pin Descriptions - Intel 82496 CACHE CONTROLLER User Manual

PINOUTS
Table 1-9. 82496 Cache Controller/82491 Cache SRAM Interface Signals
BLAST# BRDYC2#/BRDYC# MCYC# WBTYP[LRO)
BLEC# BUS# WAY WBWE# [LR1)
BOFF# MAWEA# WBA[SEC2#) WRARR#
Table 1-10. Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions
Symbol Type Part Name and Function
A[15:0)
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P Pentium™ processor Address pins. 82491 Cache SRAM Address inputs.
A[31:3)
1/0
CC
As outputs, the CPU address lines, along with the byte enables, define the
physical area of memory or 1/0 accessed. The 82496 Cache Controller
drives the inquire address to the Pentium processor on A[31 :5). Note that
82491 Cache SRAM address pin AO is always connected to VSS.
A20M#
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P When the Address bit 20 Mask pin is asserted, the Pentium processor
emulates the address wraparound at one Mbyte which occurs on the
8086. When A20M# is asserted, the Pentium processor masks physical
address bit 20 (A20) before performing a lookup to the internal caches or
driving a memory cycle on the bus. The effect of A20M# is undefined in
protected mode. A20M# must be asserted only when the processor is in
real mode.
ADS# I CC
Address Strobe signal from the Pentium processor to the 82491 Cache
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CS
SRAMs. ADS# indicates the start of a new, valid CPU bus cycle and is
0 P
functionally identical to ADSC#. The 82496 Cache Controller ADS# input
is connected to the Pentium processor ADSC# output.
ADSC# 0 P Address Strobe signal from the Pentium processor to the 82496 Cache
Controller ADS# input. ADSC# indicates the start of a CPU cycle and is
functionally identical to ADS#.
AHOLD 0 CC In response to the assertion of Address Hold, the Pentium processor will
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P stop driving the address lines (A[31 :3)), and AP in the next clock. The rest
of the bus will remain active so data can be returned or driven for
previously issued bus cycles. AHOLD is driven by the 82496 Cache
Controller to the Pentium processor AHOLD input during back-
invalidation cycles and inquire cycles.
AP
1/0 CC
Address Parity is driven by the Pentium processor with even parity
1/0
P information on all Pentium processor generated cycles in the same clock
that the address is driven. Even parity is driven back to the Pentium
processor during inquire cycles on this pin in the same clock as EADS#
by the 82496 Cache Controller to ensure that the correct parity check
status is indicated by the Pentium processor.
1-16
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