82491 Cache Sram Bus Configuration - Intel 82496 CACHE CONTROLLER User Manual

CACHE INITIALIZATION AND CONFIGURATION
intel®
Table 4-4. Memory Bus Address Control
Config Cache (Line Address)
(Subline Address) (NC)
#
Size (S,T,L) (CL,CS) Unused
MALE and MAOE# MBALE and MBAOE# pins
1 256KB
MCFA4·MCFA2, MTAG11-MTAGO, MSET10- MCFA1, MCFAO MCFA5
MSETO, MCFA6
2 256KB
MCFA4-MCFA2, MTAG11-MTAGO, MSET10- MCFA6, MCFA1, MCFAO MCFA5
MSETO
3
512KB MCFA3, MCFA2, MTAG11-MTAGO, MSET10- MCFA1, MCFAO MCFA4
MSETO, MCFA6, MCFA5
4 512KB MCFA3, MCFA2, MTAG11-MTAGO, MSET10-
MCFA5,MCFA1,MCFAO MCFA4
MSETO, MCFA6
5
512KB MCFA3, MCFA2, MTAG11-MTAGO, MSET10- MCFA6, MCFA5, MCFA4
MSETO
MCFA1, MCFAO
TAG SET LINE SUBLINE
In''''''~
l~~["+ 1~ 1~[
~"--I
I
SUBLINE
~
MBALE
LINE ADDRESS LATCH
ADDRESS
LATCH
~
MAOE#
~
MBAOE#
1"~" 1"' "
1-°"'
l~'l
MCFA,MTAG
MCFA,MSET MCFA MCFA MCFA
NOTE: ADDRESS SIGNAL CONNECTIONS ARE CONFIGURATION DEPENDENT
CDB13
Figure 4-5. Address Latching
4.2.8. 82491 Cache SRAM Bus Configuration
The 82491 Cache SRAM needs to be configured to drive either 4 or 8 MDATA lines. The
82491 Cache SRAM configuration also determines whether the cache SRAM performs 4 or 8
memory transfers per linefill. The 82491 Cache SRAM is configured through the MX4/MX8#
and the MTR4/MTR8# configuration inputs. For a given line ratio (memory bus line size /
4-8
I