Mbe - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.82. MBE#
MBE#
Memory Byte Enable
A latched version of the Pentium processor BE[7:0]# output signals.
Output from 82491 Cache SRAM (pin 32)
Synchronous to ClK
Internal Pull-up
Signal Description
The 82491 Cache SRAM includes an on-chip memory byte enable latch that replaces what
used to be a discrete component on Intel486 DX CPU-Cache Module and Chip Set. This latch
samples the Pentium processor BE# input and passes it as an MBE# (memory byte enable)
output to the bus controller.
The byte enable latching is controlled by a 82491 Cache SRAM input, BLEC#, from the 82496
Cache Controller. The latch samples BE# at each clock rising edge when BLEC# is low. When
BLEC# is high, the latch is closed and MBE# [P AR#] is driven to the corresponding CPU
BE[7:0]# level.
The MBE# output is shared with the P AR# pin and is operative following reset. For a device
configured in PARITY mode at reset time, the MBE# output function is tri-stated (PAR# is
strapped low).
MBE# is not valid during 82496 Cache Controller replacement write back, snoop write back,
and allocation cycles. The MBC must regard all CPU byte enables as active during these
cycles.
For a 512-Kbyte cache size design (16 data 82491 Cache SRAM devices), the MBC needs to
use only 8 of the 82491 Cache SRAMs to pass CPU byte enable information to the memory
system. The remaining MBE# outputs may remain disconnected.
When Driven
On the first memory bus cycle following reset deassertion, MBE# is valid with CADS#. Figure
5-27 illustrates MBE# [PAR#] timing after RESET.
ClK
SNPCYC#
MAPERR#
~ __ ~ __ ~~X~~~~I~VA~l=ID~A~I~x~I ____ ~lvA=l=ID~B~I __ ~_
I
CDB44
Figure 5-27. MBE# [PAR#] Timing After RESET
I
5-133