Snooping 82496 Cache Controller Without Invalidation Request; Snooping 82496 Cache Controller With Invalidation Request; Sync Cycles - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
Table 3-4. Snooping 82496 Cache Controller without Invalidation Request
Pres. Memory Bus CPU Bus
State Condition: Next State Activity Activity
Comments
M !SNPNCA: S MTHIT INOR Snoop hit to modified line. 82496 Cache
SNPNCA:
E
MHITM
Controller indicates tag hit and modified
hit. 82496 Cache Controller schedules a
WBCK
write back of the modified line to
memory. If non-cacheable access, stay
in
lEI
sate.
E
!SNPNCA: S MTHIT
-
If snooping by a cacheable access, indi-
SNPNCA:
E
cate MTHIT and go to shared state. If a
non cacheable access, only indicate
MTHIT, stay exclusive.
S
S MTHIT
-
I I
-
-
Table 3-5. Snooping 82496 Cache Controller with Invalidation Request
Pres. Memory Bus CPU Bus
State
Next State Activity Activity
Comments
M I MTHIT INOR, Snoop hit to modified line. 82496 Cache
BINV Controller indicates tag hit and modified
MHITM
hit. 82496 Cache Controller schedules a
WBCK
write back of the modified line to
memory. Invalidate CPU.
E
I MTHIT BINV Indicate tag hit, invalidate 82496 Cache
Controller, CPU lines.
S I MTHIT BINV Same as before
I I -
-
Table 3-6. SYNC Cycles
Pres. Memory Bus CPU Bus
State Next State Activity Activity Comments
M
E
WBCK INOR Get modified data from Pentium™
processor flush to memory.
E E -
-
Memory already synchronized
S S
-
-
Memory already synchronized
I I
-
-
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I