Intel 82496 CACHE CONTROLLER User Manual page 72

Volume 2: 82496 cache controller and 82491 cache sram data book
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CHAPTER 2
CACHE ARCHITECTURE OVERVIEW
The Pentium processor CPU-Cache Chip Set is Intel's next generation high-performance
CPU/Cache Core solution for servers and high-end desktop systems.
The 82496 Cache Controller/82491 Cache SRAM second level cache solution is an enhanced
version of the 82495DX/82490DX cache which was designed for use with the 50-MHz
Intel486™ DX microprocessor. The 82496 Cache Controller provide the enhancements needed
to support the Pentium processor's features.
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The Pentium processor CPU Cache Chip Set is comprised of a Pentium processor, a 82496
cache controller and a variable number of 82491 Cache SRAMs for a 256K or 512K byte
second level cache size. The chip set provides zero-wait-state operation on the CPU bus and
can be interfaced to a memory bus of 32, 64 or 128 bits in size using a variety of memory bus
protocols. (A 32-bit memory bus is an implementation alternative, 64 and 128 bits are
selectable configurations.)
The 82496 Cache Controller is a high-performance write-back/write-through cache controller
providing integrated tags and comparators and implementing the popular high performance
MESI cache consistency protocol.
The 82491 Cache SRAM is a high-performance dual-ported custom SRAM supporting 32, 64,
and 128-byte line sizes and optional sectoring. The tightly coupled 82496/82491 Cache SRAM
interface is optimized for speed and concurrency. The 82496 Cache Controller/82491 Cache
SRAM separates the Intel Pentium processor bus from the memory bus. The 82496 Cache
controller and memory bus can handshake synchronously, asynchronously, or with a strobed
protocol. The Pentium processor CPU Cache Chip Set interface allows for concurrent CPU
bus and memory bus operation.
The Pentium processor CPU Cache Chip Set operates at either 60 MHz or 66 MHz. The
Pentium processor is implemented in a 273 pin ceramic PGA package. The 82496 Cache
Controller is implemented in a 280 pin ceramic PGA package. The 82491 Cache SRAM is
implemented in an 84 lead PQFP package.
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