Hitm - Intel 82496 CACHE CONTROLLER User Manual

Volume 2: 82496 cache controller and 82491 cache sram data book
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HARDWARE INTERFACE
5.2.2.56.
HITM#
HITM#
Hit to a Modified Line
Indicates a hit to a Modified line in the Pentium processor data cache.
Output from Pentium processor (pin M04), Input to 82496 Cache Controller (pin
E18), Input to 82491 Cache SRAM (pin 62)
Synchronous to ClK
82491 Cache SRAM internal Pull-up
Signal Description
Refer to the Pentium™ Processor Data Book for a detailed description of this signal.
5-102
I

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