Intel 82496 CACHE CONTROLLER User Manual page 364

MEMORY BUS FUNCTIONAL DESCRIPTION
snooping. The 82496 Cache Controller checks that MAOE# and MBAOE# are sampled
inactive in order to recognize the snoop request. MAOE# is latched together with the snoop
address (MSET[1O:0], MTAG[ll:O], MCFA[6:0], MAP), SNPINV and SNPNCA. These
signals are latched by the 82496 Cache Controller's clock (not SNPCLK) rising edge, during
SNPSTB# assertion. The look-up is done immediately after SNPSTB# (clocks 2-3) since
snoops have the highest priority in the cache directory arbiter (TAGRAM arbitration).
SNPCYC#, in clock 2, indicates that snoop look-up is in progress. The results of the look-up
are driven to the memory bus via MTHIT# and MHITM# signals. Since the snoop hits a
modified line, both signals are activated (clock 3). SNPBSY# is also driven active indicating
the 82496 Cache Controller is busy with CPU bus inquires or the 82491 Cache SRAM's snoop
buffer is full. The 82496 Cache Controller will accept snoops only when SNPBSY# is inactive.
Concurrently with the memory bus activity (snoop request), the CPU issues an ADS# of a read
miss cycle (clock 1). The 82496 Cache Controller issues CADS#, CDTS# and cycle control
signals to the MBC (clock 3). Note that the CPU request look-up is done with ADS# (clocks 1-
2), while the snoop request look-up is done one clock after SNPSTB# (clocks 2-3). The MBC
samples CADS# active and waits for the memory bus to execute the pending cycle.
In clock 5, the 82496 Cache Controller issues SNPADS# and cycle control signals to the MBC
indicating a request to flush a modified line out of the cache. SNP ADS# activation causes the
MBC to abort the pending cycle. It is the 82496 Cache Controller's responsibility to re-issue
the aborted cycle after the completion of the write back, since BGT# had not yet been activated
on the CLK when SNPSTB# was sampled active.
The 82496 Cache Controller issues AHOLD (clock 5) causing the CPU to float its address
lines. The 82496 Cache Controller issues WBWE#, WBTYP and WBA. WBTYP and WBA
would be active (high) indicating to the 82491 Cache SRAMs that a snoop hit to the ARRAY
occurred. The 82491 Cache SRAM performs an ARRAY read cycle in clock 6 and thus
requires stable address and WAY at that time. Data is loaded into the 82491 Cache SRAM's
snoop buffer one clock after the ARRA Y read cycle.
The 82496 Cache Controller drives the snoop address to the CPU bus (clocks 8-16). EADS# is
activated (clock 8) in order to inquire the CPU. Since SNPINV was sampled inactive while
SNPSTB# (clock 1), the 82496 Cache Controller issues an inactive INV with EADS#. Thus
modified data from the CPU (clocks 14-17) will be written into both the ARRAY and snoop
buffer. HITM# is activated in clock 10 indicating that the line has been modified in the CPU
cache. AHOLD remains active until the inquire sequence completion. Thus AHOLD is
deactivated in clock 18 after the BLAST#.BRDYC# of the Pentium processor write-back
cycle. If HITM# would be sampled inactive in clock 10 then AHOLD would be deactivated
one clock after that, i.e. in clock 11.
Since the CPU waits for the read miss (cycle A) to be completed in order to provide the
modified data, and the MBC waits for the memory bus to execute the pending read miss (i.e.
82496 Cache Controller write-back has to be completed), a deadlock occurs. To avoid this
deadlock, the 82496 Cache Controller issues BOFF# in clock 11, causing the CPU to abort the
read miss cycle. After BOFF# is deactivated (clock 12), the CPU issues a write-back cycle
(ADS# in clock 13) in order to flush the modified data out of the cache. The 82496 Cache
Controller provides BRDY#s to the CPU in clocks 14-17. Note that WRARR# is activated,
indicating to the 82491 Cache SRAM that it must write the data to the ARRAY. With the
BLAST#.BRDYC#, the 82496 Cache Controller activates CDTS# (clock 17) indicating to the
MBC that data is available in the snoop buffer.
I
6-19