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Intel Manuals
Computer Hardware
82496 CACHE CONTROLLER
User manual
Intel 82496 CACHE CONTROLLER User Manual
Volume 2: 82496 cache controller and 82491 cache sram data book
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Table of Contents
Table Title Page
Chapter 1 Pinouts
Pentium™ Processor Pinouts
Pinout Diagrams
82496 Cache Controller Pinouts
82491 Cache SRAM Memory Pinouts
Mooe
Pentium Processor
Pentium™ Processor Pin Cross Reference by Pin Name
Pentium™ Processor/Mbc Interface Signals
Pin Cross Reference Tables
82496 Cache Controller
82491 Cache SRAM
BRIEF PIN Descriptions
Meoc
Mfrz
Mhitm
Mistb
Mken
Moclk
Mro
Msel
Mthit
Mwb/Wt
Pentium™ Processor/82496 Cache Controller Interface Signals
Pentium™ Processor/82491 Cache SRAM Interface Signals
Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions
Mx4/8
Mzbt
Pentium™ Processor CPU-Cache Chip Set Internal Pull-Up Resistors
Pentium™ Processor CPU-Cache Chip Set Glitch Free Pins
Pentium™ Processor CPU-Cache Chip Set Internal Pull-Down Resistors
Signal Interconnects on Optimized Interface
Pin States During RESET
Pentium™ Processor CPU-Cache Chip Set Output Pins
Nene
Pentium™ Processor CPU-Cache Chip Set Input Pins
Nmi
Par
Snpinv
Snpnca
Snpstb
Sweno
Sync
Tck
Tms
Toi
Trst
W/R
Way
Wb/Wt
Pentium™ Processor CPU-Cache Chip Set Input/Output Pins
Chapter 2 Cache Architecture Overview
82496 Cache Controller
Cpu/Cache Core Description
Main Features
82491 Cache Srams
Memory Bus Controller
Configuration
Physical Cache
Clocked (Asynchronous) Snoop Mode
Memory Bus Modes
Snoop Modes
Strobed Snoop Mode
Synchronous Snoop Mode
Clocked Memory Bus Mode
Pentium Processor Bus Interface
Strobed Memory Bus Mode
82496 Cache Controller/82491 Cache Sram Optimized Interface
Memory Bus Interface
Snooping Logic
Pentium™ Processor Signals Latched in the 82496 Cache Controller and 82491 Cache SRAM
Cycle Control Logic
Test
Chapter 3 Component Operation
82496 Cache Controller Cache Consistency Protocol
Write-Back Cache Designs
WRITE-THROUGH CACHE Designs
Mesi Cache Consistency Protocol Model
BASIC MESI STATE Transitions
Basic MESI State Transitions
MESI State Changes Resulting from CPU Bus Operations
Read Hit
Read Miss
Write Hit
WRITE Miss
Write Miss with Allocation
MESI State Changes Resulting from Memory Bus Masters
Snooping
CACHE Synchronization
Cacheability Attributes: PCD, MKEN
Mesi State Changes Following Cycles with Special Attributes
Write through Protocol: PWT, MWB/WT
Locked Accesses: LOCK
Read Only Accesses: MRO
CPU Bus Signals
Direct-To-Modified Attribute: DRCTM
State Transitions
Memory Bus Signals
Cycles Resulting from State Transitions
Tag State
Tag State and Cycles.resulting from State Transitions
MESI State Tables (82496 Cache Controller State Changes)
Master 82496 Cache Controller Read Cycle
Master 82496 Cache Controller Write Cycle
Snooping 82496 Cache Controller with Invalidation Request
Snooping 82496 Cache Controller Without Invalidation Request
SYNC Cycles
Inclusion
FLUSH Cycles
PRIMARY to SECONDARY CACHE Coherency
Inquire and Back-Invalidation Cycles
MESI State Tables (Pentium Processor CPU-Cache Chip Set State Changes)
Write Once Policy
MESI State Changes for READ Cycles: CPU to 82496 Cache Controller
82491 Cache SRAM Caches
MESI State Changes for WRITE Cycles: CPU to 82496 Cache Controller
82491 Cache SRAM Caches
Chapter 4 Cache Initialization and Configuration
Configuration Signal Sampling During Reset
Initialization Required for Chip Set Mode
Memory Bus Width
Physical Cache
Line Ratio
Tagram Size
Tagram Structure
Lines Per Sector (LIS)
Cache Size
Configurable Address Connections
82491 Cache SRAM Bus Configuration
4.2.10. CPU to 82491 Cache SRAM Address Configurations
82491 Cache SRAM Parity Configuration
4.2.11. Bus Driver Buffer Selection
Cache Modes
Memory Bus Modes
Clocked Mode
Configuration of Memory Bus Mode
Snoop Modes
Strobed Mode
Configuration of Snoop Mode
Description
Strong/Weak Write Ordering
Configuration
HARDWARE INTERFACE Page
MEMORY BUS CONTROLLER Considerations
Cycle Control
IDENTIFYING and EXECUTING Cycles
Cacheable Read Miss
Read Hit
Non-Cacheable Read Miss
Write Hit Lsi
Write Hit [EJ, [M]
Write Miss: no Allocation, Allocation
Locked
Replacement
Snoop Write Back
Cache-To-Cache Transfer
Read for Ownership
1/0 Cycles
FLUSH and SYNC Cycles
Special Cycles
Choosing a Snooping Mode
Snooping
Synchronous Snooping Mode
Asynchronous Snooping Mode
Strobed Snooping Mode
Snoop Operation
Snoop Blocking
When Snooping Is Not Allowed
SNOOPING DURING LOCKED Cycles
SNOOP WRITE BACK Cycles
Snooping During Split Locked Cycles
Address Integrity
Cpu Bus Address Parity
Memory Bus Address Parity
Data Control
Cpu Data Bus Transfer Control
Memory Bus Mode Selection
82491 Cache SRAM Intelligent Dual-Ported Cache Memory
82491 Cachesramdatapath
Memory Cycle Buffers
Write-Back and Snoop Buffers
MEMORY BUS CONTROL Signals
82491 CACHE SRAM PARITY Devices
Signal Synchronization
Handling of Large Caches I Larger Line Sizes
Warm Reset
5.1.10. 82496 Cache Controller Guaranteed Signal Relationships
5.1.11. 82496 Cache Controller Cycle Progress Requirements
82496 Cache Controller and 82491 Cache SRAM CRDY# Requirements
82496 Cache Controller Input Signal Recognition Requirements
82496 Cache Controller Cycle Attribute Sampling Requirements
Pentium Processor, 82496 Cache Controller, and 82491 Cache SRAM BRDY# Requirements
82496 Cache Controller Cycle Progress Signal Sampling Requirements
5.1.17. 82491 Cache SRAM Data Control Signal Requirements
5.1.18. Semaphore (Strong Write Ordering) Consistency
CONFIGURATION Signals
CYCLE ATTRIBUTE / PROGRESS Signals
Cycle Control Signals
Detailed Pentium Processor Cpu-Cache Chip Set Pin Descriptions
Signal/Category Cross-Reference
SNOOPING Signals
82496 Cache Controller/82491 Cache Sram Optimized Interface Signals
Cache Synchronization Signals
CPU Signals
Memory Address Bus and Address Control Signals
Memory Data Bus and Data Control Signals
PENTIUM PROCESSOR BUS OPTIMIZED INTERFACE Signals
Test Signals
Pentium Processor CPU-Cache Chip Set Detailed Pin Descriptions
A20M
Ads
Adsc
Ahold
Apchk
Aperr
Apic
Be#,Be[7:0]
Bgt
Blast
Ble
Blec
Boff
Bp[3:2], Pm/Bp[1 :0]
Brdy
Brdyc
Brdyc1
Brdyc2
Breq
Bt[3:0]
Bus
Buschk
Cache
Cads
Cahold
Ccache
CD/C
Cdata[7:0]
Cdts
Cfa[6:0],Set[1 0:0],Tag[11 :0]
Cfg[2:0]
Cldrv
Clk
CM/Io
Cna
Cpcd
Cpwt
Crdy
Cscyc
Cw/R
Cway
D/C
D[63:0]
Dp[7:0]
Drctm
Eads
Ewbe
Ferr
Flush
Frcmc
Fsiout
Highz
Hit
Hitm
Hlda
Hold
Ibt
Ierr
Ignne
Init
Intr
Inv
Iperr
Ken
Klock
Kwend
Lock
Lr[1 :0]
M/Io
Maldrv
Male
Maoe
Map
Maperr
Mawea
Mbale
Mbaoe
Mbe
Mbrdy
Mbt[3:0]
Mcache
Mcfa[6:0]. Mset[10:0]. Mtag[11 :0]
Mclk
Mcyc
Mdata[7:0]
Mdldrv
Wba
Wbtyp
Wbwe
Wrarr
Wwor
Chapter 6 Memory Bus Functional Description
READ Cycles
Read Hit Cycles
Read Miss Cycles
With Clean Replacement
With Replacement of Modified Line
Non Cacheable Read Miss Cycles
WRITE Cycles
Write Miss with Allocation Cycles
Locked Read-Modify-Write Cycles
Chapter 7 Electrical Specifications
Connection Specifications
Decoupling Recommendations
Maximum Ratings
Power and Ground
Specifications
Optimized Interface
Specifications
Flight Time Specification
Signal Quality
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