Intel 82496 CACHE CONTROLLER User Manual page 17

CONTENTS
Figure
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xiv
m~ P~~
Valid Delay Timings from Strobes ................................... : ....................................... 7-45
Test Timings ........................................................................................................... 7-46
Test Reset Timings ................................................................................................. 7-46
Active/Inactive Timings ........................................................................................... 7-47
Overshoot/Undershoot and Ringback Guidelines ................................................... 7-49
First Order Input Buffer ............................................................................................. 8-1
First Order Output Buffer .......................................................................................... 8-1
Input Diode Model ..................................................................................................... 8-7
Complete Input Model Including Diode ..................................................................... 8-7
Pentium™ Processor Mechanical Specifications ...................................................... 9-3
82496 Cache Controller Mechanical Specifications .................................................. 9-5
82491 Cache SRAM Mechanical Specifications ....................................................... 9-6
Technique For Measuring Tcase ............................................................................ 10-1
Boundary Scan Register Structure of a Component.. ............................................. 11-5
Device 10 Register .................................................................................................. 11-5
TAP Controller State Diagram ................................................................................ 11-9
Tables
Title Page
Pentium™ Processor Pin Cross Reference by Pin Name ........................................ 1-7
82496 Cache Controller Pin Cross Reference by Pin Name .................................... 1-9
82491 Cache SRAM Pin Cross Reference by Pin Name ........................................ 1-12
Pentium™ Processor/MBC Interface Signals .......................................................... 1-14
82496 Cache Controller/MBC Interface Signals ..................................................... 1-15
82491 Cache SRAM/MBC Interface Signals ........................................................... 1-15
Pentium™ Processor/82496 Cache Controller Interface Signals ............................ 1-15
Pentium™ Processor/82491 Cache SRAM Interface Signals ................................. 1-15
82496 Cache Controller/82491 Cache SRAM Interface Signals ............................ 1-16
Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions ......................... 1-16
Pentium™ Processor CPU-Cache Chip Set Internal Pull-Up Resistors .................. 1-36
Pentium™ Processor CPU-Cache Chip Set Internal Pull-Down Resistors ............. 1-36
Pentium™ Processor CPU-Cache Chip Set Glitch Free Pins ................................ 1-36
Signal Interconnects on Optimized Interface .......................................................... 1-37
Pin States During RESET ....................................................................................... 1-39
Pentium™ Processor CPU-Cache Chip Set Output Pins ........................................ 1-40
Pentium™ Processor CPU-Cache Chip Set Input Pins ........................................... 1-43
Pentium™ Processor CPU-Cache Chip Set Input/Output Pins ............................... 1-47
Pentium™ Processor Signals Accessible by the MBC .............................................. 2-7
Pentium™ Processor Signals Latched in the 82496 Cache Controller and
82491 Cache SRAM ................................................................................................. 2-8
Basic MESI State Transitions ................................................................................... 3-4
Master 82496 Cache Controller Read Cycle .......................................................... 3-14
Master 82496 Cache Controller Write Cycle ........................................................... 3-15
Snooping 82496 Cache Controller without Invalidation Request. ........................... 3-16
Snooping 82496 Cache Controller with Invalidation Request... .............................. 3-16
SYNC Cycles .......................................................................................................... 3-16
FLUSH Cycles ........................................................................................................ 3-17
MESI State Changes for READ Cycles: CPU to 82496 Cache Controller/
82491 Cache SRAM Caches .................................................................................. 3-20
MESI State Changes for WRITE Cycles: CPU to 82496 Cache Controller/
82491 Cache SRAM Caches .................................................................................. 3-21
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