Master 82496 Cache Controller Write Cycle - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
Table 3·3. Master 82496 Cache Controller Write Cycle
Pres. Mem Bus CPU Bus
State Condition: Next State Activity Activity Comments
M
!LOCK: M
-
SRUP, Write hit. Write to cache. Allow
!WT Pentium™ processor to perform
internal write cycles (Enter into [E),
[M) states).
LOCK: M WTHR SRUP, Locked Cycle. Write-Through updat-
!WT ing cache SRAM. Most updated
copy of the line is still owned by
82496 Cache Controller. All Locked
write cycles are posted.
E !LOCK: M
-
SRUP, Write hit. Update SRAM. Let
!WT Pentium processor execute internal
write cycles.
LOCK: E WTHR SRUP Lock forces cycle to memory bus.
Main memory remains updated.
S TRO:S WTHR
-
Read-Only. Data is not updated in
cache. Write Through cycle to
memory bus is performed.
ITRO.(PWT +MWT +LOCK): S WTHR SRUP
Not Read-Only. Write cycle with
write through attribute from CPU or
memory bus. Locked cycles.
ITRO. IPWT. ILOCK. IMWT. IDRCTM: WTHR SRUP Not Read-Only. No write-through
E
cycle, no lock request. Allow going
into exclusive state.
!TRO.IPWT.!LOCK.IMWT.DRCTM: WTHR SRUP Not Read-Only. No write-through
M cycle, no lock request allow going
into exclusive state. DRCTM#
forces final state to M.
I
PCD+IMKEN+PWT +LOCK: I WTHR
-
Write Miss Non-Cacheable, Write-
Through, locked cycle.
IPCD.MKEN.IPWT.ILOCK.IMRO: I WTHR
-
Write Miss with allocation. After the
Allocation Final State
ALLOe
write cycle, a line fill (allocation) is
-
scheduled. Normal allocation final
MWT:S
state is a function of the line fill
attributes. If MRO# is asserted, an
IMWT.IDRCTM: E WTHR allocation to the [S] state will occur,
IMWT.DRCTM: M
ALLOe
TRO bit is set, and attributes are
ignored.
IPCD.MKEN.IPWT.ILOCK.MRO:I
Allocation Final State: S
NOTE: The WBIWT# pin will be Write-Back (HIGH) for reads or writes to [M) state lines and for writes to [EI
state lines. On all other states, the Pentium processor will be forced to perform Write-Through cycles. This
mechanism will make sure that any Pentium processor write cycle is seen at least once on the CPU bus
(Write Once protocol).
I
3-15