Mawea - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.79.
MAWEA#
MAWEA# Memory Bus Array Write Enable or Allocation
Indicates that the data should be written or an allocation should occur.
Output from 82496 Cache Controller (pin R18), Input to 82491 Cache SRAM (pin
41)
Synchronous to ClK
Signal Description
During read cycles, MAWEA# indicates to the 82491 Cache SRAM that data supplied from
memory should be written to the array one CLK after CRDY# (the linefill will be executed
then). During write cycles, MA WEA# indicates that the 82491 Cache SRAM should schedule
an allocation cycle following the current write cycle. The data will be written to the 82491
Cache SRAM array one CLK after the CRDY# of the allocation. MA WEA# is active 1 CLK
after KWEND# for cacheable read miss cycles or write through with potential allocation
cycles.
Relation to Other Signals
None.
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