Intel 82496 CACHE CONTROLLER User Manual page 348

MEMORY BUS FUNCTIONAL DESCRIPTION
CycleB
In clock 4, the Pentium processor issues an ADS# (cycle B) with a burst length of four
transactions. A CPU line-fill is executed in clocks 5-8 (burst length=4) since CACHE# was
sampled active (clock 4). As a result of the blind NA# (clock 5), the CPU issues another ADS#
(cycle C) in clock 7 (pipe lined ADS#).
Cycle C
In clock 7 the CPU issues the ADS# for cycle D due to NA# activation in clock 5. As a result
of the MRU miss, the 82496 Cache Controller the correct WAY to the 82491 Cache SRAM
(using the WRARR# and WAY signals - not shown). Upon sampling WRARR# active, the
82491 Cache SRAM will update its internal MRU bit with the way information presented by
the WAY signal. This information is also used by the 82491 Cache SRAM to select from its
CPU buffer the data corresponding to the correct way. The 82491 Cache SRAM drives the
CPU data bus by the end of clock 9. Note that the wait-state caused by the MRU miss is hidden
due to the pipeline.
KEN# is driven high to the CPU in the CLK of BRDYC# active (clock 9) in response to the
CACHE# signal being sampled inactive (clock 7).
Cycle D
In clock 11 (2 CLKs after the previous NA#), the CPU issues another pipelined ADS# (cycle
D). In this cycle a wait-state is added (clock 12) due to the MRU miss. WB/WT# is driven high
to the Pentium processor to indicate that the read hit was to a line in the Modified state.
Cycle E
In clock 14 the CPU issues a pipelined ADS# (cycle E) due to a previous NA# (clock 12).
CACHE# is sampled active (clock 14). Due to the 1.5 level of pipeline, the 82496 Cache
Controller waits until the last BRDYC# of the previous cycle (Cycle D in clock 16) to begin
the four transfers for cycle E.
Note that in all cycles BLEC# is deactivated immediately after ADS#. It activated again in the
next clock, since all cycles are hits.
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