Intel 82496 CACHE CONTROLLER User Manual page 251

Volume 2: 82496 cache controller and 82491 cache sram data book
Table of Contents

Advertisement

HARDWARE INTERFACE
Relation to Other Signals
Pin Symbol
Relation to Other Signals
MALE
MALE and MAOE# together provide full control over the 82496 Cache Controller
MAP
line address output latch and the memory bus address parity (MAP) latch.
MBAOE#
MAOE# and MBAOE# together control the entire 82496 Cache Controller memory
bus address.
SNPSTB#
If MAOE# is active when SNPSTB# is asserted, the snoop request is ignored by
the 82496 Cache Controller.
5-126
I

Advertisement

Table of Contents
loading

This manual is also suitable for:

82491 cache sramPentium

Table of Contents