Intel 82496 CACHE CONTROLLER User Manual page 47

PINOUTS
Table 1-10. Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions (Contd.)
Symbol Type Part Name and Function
MBAOE#
I
CC
82496 Cache Controller Memory Bus Sub-Line Address Output Enable
functions like MAOE# but only controls the 82496 Cache Controller sub-
line addresses. If MBAOE# is active (low), the 82496 Cache Controller
drives the sub-line portion of the address onto the memory bus.
Otherwise, the 82496 Cache Controller's sub-line address is driven to the
hi-z state. MBAOE# is also sampled during snoop cycles. If MBAOE# is
sampled inactive in conjunction with SNPSTB#, snoop write back cycles
begin at the sub-line address provided. If MBAOE# is sampled active with
SNPSTB#, snoop write back cycles begin at sub-line address O. A
separate sub-line control input is provided because the 82496 Cache
Controller only provides the starting sub-line address.
MBE#
0
CS The 82491 Cache SRAM Memory Byte Enable output is a latched
version of the Pentium processor byte enable outputs, BE[7:0]#. The
memory cycle byte enables (MBE#) are always valid either with or one
CLK after CADS#.
MBE# shares a pin with the 82491 Cache SRAM Configuration pin PAR#.
MBRDY# I CS In clocked memory bus mode, Memory Bus Ready is used to clock data
into and out of the 82491 Cache SRAM . When active (LOW), MBRDY#
indicates that the 82491 Cache SRAM will increment the burst counter
and output or accept the next data upon the rising edge of MCLK (or
MOCLK for writes, if applicable). MBRDY# is qualified by MSEL#.
MBRDY# shares a pin with the 82491 Cache SRAM input signal MISTB.
MBT[3:0]
0
CC
The Memory Branch Trace Address signals echo the Pentium processor
BT[3:0] bits which provide bits 2:0 of the branch target linear address
(MBT[2:0]) and the default operand size (MBT3) during a branch trace
message special cycle. MBT[3:0] must be pulled low with an external
resistor for proper cache operation.
MCACHE#
0
CC 82496 Cache Controller Internal Cacheability is driven during read cycles
to indicate whether the current cycle is potentially cacheable in the 82496
Cache Controller /82491 Cache SRAM. During write operations,
MCACHE# is only active for write-back cycles. MCACHE# is inactive
during I/O, special and locked cycles.
MCFA[6:0] I/O CC Memory Bus Configurable address lines
MSET[10:0] I/O CC Memory bus SET number
MTAG[11:0] I/O CC Memory bus TAG bits
The Memory Address lines are used along with the 8 MBE#s to define
the areas of memory or I/O to be accessed. They are driven during normal
memory bus cycles and are inputs during snoop operations.
MCLK I
CS
Memory Bus Clock is the memory bus clock input to the 82491 Cache
SRAM while in clocked memory bus mode. Here, memory bus signals
and data are sampled on the rising edge of MCLK. During clocked
memory bus writes, data is driven with respect to MCLK or MOCLK,
depending on the configuration. MCLK inputs to each 82491 Cache SRAM
must be within proper skew specifications.
MCLK shares a pin with the Configuration signal MSTBM.
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