Intel 82496 CACHE CONTROLLER User Manual page 293

HARDWARE INTERFACE
5.2.2.106. MZBT#
MZBT# Memory Zero Base Transfer
Forces cycles to begin at sub-line address O.
Input to 82491 Cache SRAM (pin 21)
Synchronous to MCLK or Asynchronous (Strobed Mode)
Internal Pull-up
Signal Description
MZBT# is an input to the 82491 Cache SRAM that forces a memory bus read or write cycle to
begin with burst address 0 regardless of the CPU-generated or snoop initiated burst address. In
systems that never force a zero-based transfer, MZBT# may be driven HIGH after RESET.
MZBT# is sampled before the transfer begins with MSEL# inactive or both MSEL# and
MEOC# active.
Once sampled active, data input to the 82491 Cache SRAM's data bus begins at burst address 0
and continue through 8, 10, etc. (for 64 bit memory buses) or through 10,20, etc. (for 128 bit
memory buses). If the CPU requests a burst location other than 0, the MBC must hold off any
BRDY# until that bursted item is read from the memory bus.
When Sampled
In clocked mode, MZBT# is sampled in two places. First, MZBT# is sampled on all MCLK
rising edges in which MSEL# is sampled inactive. Once MSEL# is sampled active, the value
of MZBT# that was sampled one MCLK before is used for the next transfer. Second, MZBT#
is sampled on MCLK rising edges where MEOC# is sampled active with MSEL# active. The
MZBT# value sampled is used for the next transfer. This allows MSEL# to stay asserted
between transfers, if needed (see Figure 5-30).
In clocked memory bus mode, MZBT# must follow set-up and hold times to all MCLK edges
where MSEL# is sampled inactive or MEOC# is sampled active with MSEL# active.
In strobed mode, MZBT# is sampled with the same signals. First, it is sampled with the falling
edge of MSEL#. Second, it is sampled with the falling edge of MEOC# when MSEL# is
active.
In strobed memory bus mode, MZBT# must meet set-up and hold times to MSEL# falling edge
and MEOC# falling edge if MSEL# is active.
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