Lines Per Sector (Lis) - Intel 82496 CACHE CONTROLLER User Manual

CACHE INITIALIZATION AND CONFIGURATION
ADDRESS
TAG
I
SET
I
DW BYTE
I
L
TAG TAG DATA
DATA
~
~
~
r-
-
· .
·
.
· .
·
.
· . · .
· .
· .
·
.
WW
WAY 0
,~
,If
WAY 1
WAYO~ ~WAY1
CACHE
CACHE
DIRECTORY
=
DIRECTORY
=
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DATA OUT
HIT/MISS
CDB53
Figure 4-4. Two-Way Set Associative Tag RAM Structure
The 82496 Cache Controller tagRAM memory can be configured in either 2K or 4K sets. A set
is selected by direct mapping of 11 or 12 bits of the physical address, called the set-address bits
(SET[10:0]). Each set contains two ways. Tags are composed of the additional physical
address bits needed to identify the line(s) in the sector.
Figure 4-4 shows how the tag bits are stored in the tag array of the 82496 Cache Controller.
The sectors corresponding to the tag bits are stored in the 82491 Cache SRAMs. Each sector
has a tag. For 4K sets, there are 8K tags with 15 bits per tag. For 2K sets, there are 4K tags
with 14 bits per tag.
A read only bit and two state bits are stored with each tag in the tag array of the 82496 Cache
Controller. The read-only bit provides compatibility with certain shadow ROM techniques.
The two state bits identify which lines contain valid data, help to implement deferred memory
updating, and maintain consistency among multiple caches.
The explanation above assumes one line per sector. For configurations which use two lines per
sector, the most significant DW bit is used to select which line in the sector is being accessed.
4.2.5.
Lines per Sector (LIS)
The 82496 Cache Controller/82491 Cache SRAM can be configured as non-sectored (L/S=I)
or with two lines per sector (L/S=2). If L/S=2, the 82496 Cache Controller contains one tag
and Read-Only bit for each pair of consecutive cache lines. Each line has its own set of MESI
state bits. This configuration enables a single line to be filled during line fills or written back
during snoop hits. Both lines are invalidated and written back during replacements if both lines
4-6
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