Cscyc - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.41. CSCYC
CSCYC latched Pentium processor SCYC pin
A latched version of the Pentium processor SCYC output signal.
Output from 82496 Cache Controller (pin E01)
Synchronous 10 ClK
Signal Description
CSCYC reflects the Pentium processor SCYC output signal during a CPU LOCKed cycle on
the memory bus. CSCYC is inactive (LOW) during write-backs, snoop write-backs, and
allocations.
When Driven
CSCYC is valid from the CLK of CADS# and SNPADS# until the CLK of CRDY# or CNA#.
Relation to Other Signals
Pin Symbol
Relation to Other Signals
CADS#
Address and cycle specification signals (i.e., APIC#, CCACHE#, CD/C#, CM/IO#,
CPCD, CPWT, CSCYC, CW/R#, CWAY, KlOCK#, MAP, MBT[3:0j, MCACHE#,
MCFA, MSET, MTAG, NENE#, PAllC#, RDYSRC, and SMlN#) are valid with
CADS#.
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