Memory Cycle Buffers; Write-Back And Snoop Buffers - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
determines which buffer and, more specifically, which buffer slice is on the bus. When
MBRDY# and MSEL# are asserted, a memory burst counter is incremented, allowing the
MUX to select the next buffer slice.
The memory burst counter follows the CPU burst order according to the sub-line address of the
initial sliCe. When MZBT# is sampled active by the 82496 Cache Controller, the CPU initiated
burst order is ignored and the memory bus read or write begins with burst address O. When the
MBC finishes with one buffer, MEOC# is asserted to switch the MUX to the next buffer in
line. MEOC# also resets the counter and latches the last data slice
(if
used instead of the last
MBRDY# or MISTB/MOSTB).
On the CPU side, the 82491 Cache SRAM contains two CPU buffers and a MUX to each. A
CPU buffer captures data from the appropriate memory buffer or array and transfers it to the
CPU. The MUX selects the data slice to be MUXed to the CPU bus. The counter associated
with the selected MUX is incremented by BRDY#.
The 82491 Cache SRAM array contains a MUX that selects the WAY that data will be read
during hit cycles, based on the MRU algorithm. This MUX is used during write cycles to write
data according to the proper WAY.
5.1.6.2.
MEMORY CYCLE BUFFERS
The 82491 Cache SRAM contains two memory cycle buffers which are used for memory
reads, allocations and memory writes. The buffers have a maximum configured width of 128
bytes (distributed over the 16 data 82491 Cache SRAMs). The 82491 Cache SRAM uses the
buffers in an alternating fashion, using the buffer available when the other has a posted write
or is being used for a memory read.
During allocation cycles, read for ownership may be implemented using the MFRZ# signal. If
MFRZ# is sampled active during a write cycle with PALLC# active, the memory cycle buffer
freezes write data so that the subsequent line fill loads data to occupy the surrounding
locations.
In
this way, the write cycle need not be written to memory. The MBC must complete
this "dummy" write cycle to the 82496 Cache Controller (i.e., provide BGT#, KWEND# and
CRDY#). Following the line fill, the line must be tagged as Modified.
5.1.6.3. WRITE-BACK AND SNOOP BUFFERS
The write back and snoop buffers are 128 bytes wide to accommodate the maximum 82491
Cache SRAM line length. The write back buffer is used when replaced data must be written
back to main memory (including FLUSH and SYNC cycles) while the snoop buffer is used
when data must be written out on a snoop hit to a modified line.
Before a line fill completes, the 82496 Cache Controller determines whether it must remove a
modified line to free space for a line fill. If necessary, the modified line is placed in the write-
back buffer and the line fill is filled via a memory cycle buffer. If the line fill is non-cacheable,
the contents of the memory cycle buffer and the replacement write-back buffer are discarded,
and the 82491 Cache SRAM array value is as it was before the line fill.
Line-fill, replacement write-back, FLUSH, and SYNC cycles are not atomic. If a snoop request
is initiated between cycles, the write-back buffer can be snooped, and data can be written
directly out as needed.
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