Bt[3:0] - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.22.
BT[3:0]
BT[3:0] Branch Trace Address bits
Provides bits 0-2 of the branch target linear address and the default operand size
during a Branch Trace Message Special Cycle.
Output from Pentium processor (pins: W20, TO?, W21, T08)
Input to 82496 Cache Controller (pins: A10, A12, A14, A16)
Synchronous to ClK
Signal Description
Refer to the Pentium™ Processor Data Book for a detailed description of these signals.
The system designer has the option to either connect or leave unconnected the BT[3:0] pins
between the Pentium processor and the 82496 Cache Controller.
If the BT[3:0] pins are left unconnected between the Pentium processor and the 82496
Cache Controller, the MBT[3:0] outputs of the cache controller reflect a latched version of
the BT[3:0] inputs during Branch Trace Message Special Cycles.
If the BT[3:0] pins are left unconnected between the Pentium processor and the 82496
Cache Controller, external pulldowns must be connected to the BT[3:0] pins of the 82496
Cache Controller during normal operation. The system designer may then monitor the BT[3:0]
outputs of the Pentium processor during Branch Trace Message Special Cycles.
Relation to Other Signals
Pin Symbol Relation to Other Signals
MBT[3:0] The 82496 Cache Controller MBT[3:0] outputs reflect the BT[3:0] inputs during
Branch Trace Message Special Cycles.
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