Intel 82496 CACHE CONTROLLER User Manual page 276

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HARDWARE INTERFACE
5.2.2.93. MFRZ#
MFRZ# Memory Data Freeze
Freezes memory write data in 82491 Cache SRAM buffer.
Input to 82491 Cache SRAM (pin 24)
Synchronous to MCLK or asynchronous (strobed mode)
Internal Pull-up
Signal Description
MFRZ# is a 82491 Cache SRAM input that causes the 82491 Cache SRAM to freeze write
data in the current memory cycle buffer. The subsequent allocation fills around the data from
the previous write cycle. MFRZ# is provided so that an actual write to memory need not be
done in case of an allocation. Using MFRZ# to perform this "dummy write cycle" requires that
the MBC put the allocated line in the [M] state. Note that if MFRZ# is sampled active, the
MEOC# will not switch memory cycle buffers (i.e., the allocation will occur in the same 82491
Cache SRAM buffer).
PALLC# must be active and MKEN# must be returned active in order for the write cycle to be
turned into an allocation (i.e., MFRZ# is ignored if either PALLC# or MKEN# are inactive).
MFRZ# is sampled when MEOC# goes active at the end of the write cycle. The subsequent
line fill is then filled around the write data to complete the allocation (see Figure 5-28).
MCLK
~
MEOC#
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MFRZ# Sampled
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CDB99
NOTES:
1. For strobed mode, MFRZ# is still sampled with respect to MEOC# as shown above; however, MCLK is
not active.
2. The MEOC# above occurs at the end of a write cycle. A linefill cycle follows this wnte cycle.
Figure 5-28. MFRZ# Sampling
In clocked memory bus mode, MFRZ# is sampled with the MCLK rising edge in which
MEOC# is sampled active for all CPU write cycles. MFRZ# need only follow a proper set-up
and hold time in this situation. Refer to Chapter 6 for an example of a read-for-ownership
cycle.
In strobed mode, MFRZ# is sampled with the falling edge of MEOC# for write cycles. MFRZ#
need only follow a proper set-up and hold time in this situation.
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