Intel 82496 CACHE CONTROLLER User Manual page 29

PINOUTS
Table 1·1. Pentium™ Processor Pin Cross Reference by Pin Name (Contd.)
Address Data Control
A27 V21 024 B10 056 H21 OPO H04 PWT S03
A28 V06 025 C08 057 F20 OP1 COS
RIS#
R18
A29 V20 026 C11 058 J18 OP2 A09 RESET L18
A30 W05 027 009 059 H19 OP3 008 SCYC R04
A31 V19 028 011 060 L19 OP4 018 SMI# P18
029 C09 061
K19 OP5 A19
SMIACT#
T05
BTO T08 030 012 062 J19 OP6 E19 TCK T04
BT1 W21 031 C10 063 H18 OP7 E21
TOI
T21
BT2 T07 EAOS# M03 TOO S21
BT3 W20
EWBE#
A03
TMS P19
FERR# H03 TRST# S18
FLUSH#
U02
W/R#
N03
WB!WT# M02
VCC VSS
A04 C01 N21 W08 B05 B15 H02 L20 020
V10
A05 001 POi W09 B06 B16 H2O M01 R02 Vii
A06 E01 P21 W10 B07 B17 J01 M20 R20 V12
AD7 F01 001 W11 B08 B18 J20 N02 S02 V13
AD8 F2i
018
W12 B11 E02 K01 N20 T02 V14
A11 G01
021
W13 B12 F02 K02 P02 V07 ViS
A12 G21 R01
Wi4 B13 G02 K20
P20
V08
V16
A13 HOi R21 W15 B14 G20 L01 002 V09 Vi7
A14 J21 S01 W16 V18
A15 K21 T01 W17
A16 L21 U01 W18
A17 M21 W06
NC: 019
S19 R19 Ti8
A18 N01 W07
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