Blast - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.12.
BLAST#
BLAST# Burst Last
Indicates the end of a burst cycle.
Output from 82496 Cache Controller (pin 016), Input to 82491 Cache SRAM (pin
59)
Synchronous to CLK
Signal Description
BLAST# indicates that the current CPU BRDY# or BRDYC# is the last of the burst sequence.
The 82496 Cache Controller will decode cycle length information from the Pentium processor
CACHE# and D/C# pins, and from the MKEN# and MRO# inputs from the MBC. It will drive
BLAST# as an output to provide the burst last indication to the 82491 Cache SRAMs.
Refer to Table 5-1 in section 5.1.1.1 for cycle identification and length details.
When Driven
BLAST# is driven with the last BRDYC# of a burst sequence or with the single BRDYC# of a
non-burst cycle.
Relation to Other Signals
Pin Symbol Relation to Other Signals
BROYC# BLAST# qualifies the BROYC# signal to the 82491 Cache SRAMs.
5-50
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