Intel 82496 CACHE CONTROLLER User Manual page 327

HARDWARE INTERFACE
5.2.2.134. SWEND#
SWEND# Snoop Window End
Closes Snooping Window.
Input to 82496 Cache Controller (pin R02)
Synchronous to ClK
Internal Pull-up
Signal Description
SWEND# closes the snooping window (which started with CADS#) by causing MWB/WT#
and DRCTM# to be sampled. DRCTM# and MWB/WT# can be determined after the other
C5Cs have been completely snooped.
The 82496 Cache Controller blocks snoop responses between BGT# and SWEND# activation.
Accordingly, the sooner SWEND# is asserted, the faster snoop cycles can be completed.
All CPU-generated write cycles and cache read miss cycles cause memory bus snoops.
SWEND# may be activated once snooping has completed for these cycles. SWEND#
activation causes the internal tags of the 82496 Cache Controller cache controller to change
state, as needed, for the current cycle_ DRCTM# and MWB/WT# influence the state change
decision.
When Sampled
SWEND# need only be active for cycles requiring DRCTM# and MWB/WT# to be sampled
(i.e., cacheable read misses, allocations, and write cycles with potential upgrade).
If a cycle does not specifically require SWEND#, and SWEND# is not returned, snooping is
blocked from BGT# to CRDY#. For this reason, it may be more efficient to always return
SWEND#.
SWEND# should be issued with or after KWEND#, when KWEND# is applicable. For cycles
that do not sample KWEND#, SWEND# is sampled with or after BGT#. Once SWEND# is
sampled active, it is ignored until CADS# of the next cycle or CRDY# of the current cycle (the
latest of the two).
Snoop response is blocked between BGT# and SWEND#. If a snoop is initiated between
BGT# and SWEND#, then the snoop lookup (SNPCYC#) is performed 2 eLKs after
SWEND# activation. Any subsequent snoop write-back begins after CRDY#.
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