Intel 82496 CACHE CONTROLLER User Manual page 105

COMPONENT OPERATION
1. The locked write cycle always begins and ends with the Pentium processor cache line in state [I]. See
Note 1 in the previous table.
2. The 82496 Cache Controller only returns WBIWT# high on unlocked write hits to [M] and [E].
3. The Pentium processor will not perform allocations on write cycles.
4. The Pentium processor cache state will not change. The 82496 Cache Controller cache line state will
go to [E] if MWBIWT#=1 and DRCTM#=1. The 82496 Cache Controller cache line state will go to [M] if
MWBIWT#=1 and DRCTM#=O. The 82496 Cache Controller cache line state will remain in [S] if
MWBIWT#=O.
Table 3-10. MESI State Changes for SNOOP Cycles: 82496 Cache Controller/82491 Cache
SRAM to CPU Caches
To From Mem
CPU Bus
I S S
N N N N
V P P
0
Initial Final Initial
N
I Final Memor t
State of State of CPU Bus State of C
N
State of yBus e
CPU CPU Activity Cache A
V
Cache Activity s
M 0
S
INOR,WB
M
0 0
S
SWB
M 1 I INOR,BINV,WB
M
x
1 I SWB
M 0 S INOR,WB
M
1
0 E SWB
E 0
S
INOR
M
0 0 S SWB
E
1 I INOR,BINV
M
x
1 I
SWB
E 0 S INOR
M
1 0
E
SWB
5 0 5 INOR M 0 0 5 SWB
S
1 I INOR,BINV M
x
1 I SWB
S
0
S
INOR M 1 0 E SWB
I 1 I INOR,BINV M
x
1 I SWB
I 0 I INOR
M
0
0
S SWB
I
0
I INOR
M 1 0
E
SWB
5 0 S None
E 0 0
S
None
S
1 .
I BINV
E
x
1 I None
S
0
S None
E
1
0 E None
I 1 I BINV
E
x
1 I None
I 0 I None E 0 0 S None
I
0 I None
E
1 0
E
None
S
0 5 None S
x
0 S None
S 1 I BINV S
x
1 I None
I 1 I BINV S
x
1 I None
I 0
I None S
x
0
S
None
I
x
I None
I
x x
I None
3-22
I