Intel 82496 CACHE CONTROLLER User Manual page 315

HARDWARE INTERFACE
5.2.2.125. SMLN#
SMlN# Same Line
Current cycle address in same 82496 Cache Controller line as previous cycle.
Output from 82496 Cache Controller (pin D07)
Synchronous to ClK
Signal Description
SMLN# indicates that a given memory cycle accesses the same line in the 82496 Cache
Controller's second-level cache as the previous memory cycle. SMLN# can be used by the
MBC to selectively activate its SNPSTB# signal to other caches in the system. In this way, for
example, back-to-back snoop hits to the same line may be snooped only once.
SMLN# must be ignored by the MBC if the memory bus accesses to the same page are not
consecutive. For example, if a snoop write back cycle is issued between two normal memory
bus cycles, the SMLN# signal may go active, but has no meaning since the snoop address
interfered with the "same line" address checking.
When Driven
SMLN# is asserted with CADS# and SNPADS# and remains valid until CNA# or CRDY#.
Relation to Other Signals
Pin Symbol Relation to Other Signals
CADS#
Address and cycle specification signals (i.e., APIC#, CCACHE#, CD/C#, CM/IO#,
CPCD, CPWT, CSCYC, CW/R#, CWAY, KLOCK#, MAP, MBT[3:0j, MCACHE#,
MCFA, MSET, MTAG, NENE#, PAlLC#, RDYSRC, and SMlN#) are valid with
CADS#.
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