Intel 82496 CACHE CONTROLLER User Manual page 281

HARDWARE INTERFACE
5.2.2.97.
MOCLK
MOClK Memory Data Output Clock
Separate ClK reference for memory data output.
Input to 82491 Cache SRAM (pin 27)
Asynchronous
Internal Pull-up
Signal Description
MOCLK is a latch enable for the 82491 Cache SRAM memory data outputs (MDATA[7:0]),
and controls the operation of a transparent latch. When MOCLK is HIGH, the data bus is
driven from MCLK. When low, data bus outputs are latched. MOCLK may only be used in
clocked memory bus mode and only affects output data. The MOCLK input is provided so that
a greater memory data minimum output hold time can be obtained (e.g. relative to MCLK). As
MOCLK is skewed relative to MCLK, MDATA hold time and output valid delay skews with
it. The maximum MOCLK delay allowed is equal to the MCLK high time.
To be used effectively, the MOCLK input must be skewed from MCLK. Figure 5-29 shows
how MOCLK can increase the hold time of the output burst data.
When Sampled
MCLK
MOCLK
MDATA
MBRDY#
~!
1 , . . - - - - " - - - -
CDB47.
Figure 5-29. Increasing Hold Time of Output Burst Data
MOCLK is sampled during and after RESET to determine whether output data should be
driven from MCLK or MOCLK.
If MOCLK is toggling, it controls the memory data outputs.
If
HIGH or LOW, data is driven from MCLK alone. Input data is never referenced to MOCLK.
In strobed memory bus mode the MOCLK signal becomes MOSTB. MOCLK is only used in
clocked memory bus mode.
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